Embodiments of the present invention relate generally to a multilayered organic substrate material used as a support substrate for electronic components and, more particularly, to forming a dielectric layer on the multilayered organic substrate material.
Electrical circuits, which may include electronic components, such as integrated circuits(ICs), resistors, capacitors, and inductors, are often supported by organic substrates. The organic substrates may also support conductive traces for conveying electric current to the terminals of the electronic components. Multilayer substrates include alternating layers of conductive and organic materials. The conductive layers comprise conductive traces interconnecting the electronic components. The conductive layers may be electrically interconnected by means of conductive vertical interconnects, such as vias that pass through adjacent organic layers of the multilayer structure or by electrically conductive vias such as plated through holes that pass through the entire substrate and are electrically continuous with selected conductive layers. The organic layers often serve as dielectric layers on the multilayered substrates that support electronic components.
In some power delivery applications, it may be desirable to have low loop inductance between the conductive traces. For example, in a multilayer substrate, some conductive layers of the substrate may serve as power planes, and others may serve as ground planes, depending on the operational requirement of the application. In such cases it may be desirable for the power delivery current loop to have low inductance. For example, in the case of high speed microprocessors, the rapid switching of transistors can cause large transient voltage drops in the power supply voltage, if the inductance of the power delivery loop is too high. These voltage drops can significantly degrade the microprocessors"" speed and performance.
In general, the loop inductance between conductive layers in a multilayer organic substrate depends on the thickness of the dielectric layer formed between the two conductive layers. As the thickness of the dielectric layer increases, the loop inductance between the two conductive layers increases. In general, the loop inductance of a conductive path is related to the cross-sectional area between power delivery and ground return paths. In the case of a multilayer organic substrates, this cross-sectional area depends on the thickness of the dielectric layer separating power and ground planes, and on the spacing between vias or through-vias (plated-through vias) that make connections between layers in the multilayer organic substrate. Therefore, to achieve lower loop inductance between conductive layers in a multilayer organic substrate, the thickness of the dielectric layer formed between conductive traces has to be reduced.
The thickness of the dielectric layer formed on a flat multilayered substrate using present fabrication techniques, such as liquid coating and dry film laminations, is about 20 microns or higher. In contrast, the thickness of the dielectric layer formed in a through-via using current fabrication techniques, such as a double-drilling process, is in the range of about 75 to 100 microns. Reducing the thickness of the dielectric layers lower than 20 microns if formed on a flat surface and lower than 75 microns if formed in a through-via, increases the risk of having pin holes and step coverage problems in the dielectric layer. Pin holes and step coverage problems in the dielectric layer can result in shorts between the two conductive traces during operation. Pin holes are microscopic holes in the dielectric layer that can become filled with conductive material, resulting in shorts between power and ground planes during operation. Step coverage is a measure of how conformal the coating is. If step coverage is poor, extreme thinning of the dielectric can occur at sharp edges, such as at the corners of conductive traces. Both pin holes and step coverage problems can cause low manufacturing yields and can be points of failure in the field, resulting in reliability problems.
Therefore, there is a need in some power delivery applications for an improved fabrication technique that provides a thinner dielectric layer free from pin holes and step coverage problems to achieve lower loop inductance values between conductive layers in a multilayered organic substrate.